// `include "sort_32_u8.v"
`default_nettype none
module tb_sort_32_u8;
parameter W_DATA = 8 ;
parameter NUM    = 32;
// port
reg               clk     ;//系统时钟
reg               rst_n   ;//系统异步复位，低电平有效
reg               vld_in  ;//输入数据有效指示
reg  [W_DATA-1:0]   din_0 ,din_1 ,din_2 ,din_3 ,din_4 ,din_5 ,din_6 ,din_7 ,din_8 ,din_9   ,
                    din_10,din_11,din_12,din_13,din_14,din_15,din_16,din_17,din_18,din_19  ,
                    din_20,din_21,din_22,din_23,din_24,din_25,din_26,din_27,din_28,din_29  ,
                    din_30,din_31  ; //输入数据0，输入数据1，……， 输入数据31
wire              vld_out ;//输出数据有效指示 
wire [W_DATA-1:0]   dout_0 ,dout_1 ,dout_2 ,dout_3 ,dout_4 ,dout_5 ,dout_6 ,dout_7 ,dout_8 ,dout_9  ,
                    dout_10,dout_11,dout_12,dout_13,dout_14,dout_15,dout_16,dout_17,dout_18,dout_19 ,
                    dout_20,dout_21,dout_22,dout_23,dout_24,dout_25,dout_26,dout_27,dout_28,dout_29 ,
                    dout_30,dout_31  ; //输出数据0，输出数据1，……， 输出数据31


localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
    $dumpfile("sim/build/tb_sort_32_u8.vcd");
    $dumpvars(0, tb_sort_32_u8);
end

initial begin
    // Initialize Inputs
    clk = 0;
    rst_n = 0;
    // Wait 10 ns for global reset to finish
    @(posedge clk);
    rst_n = 1; 
    // Add stimulus here
    // for (j = 0; j<NUM; j++) begin
    //     din_[j] = data_i[j] ;
    // end
    din_0  = 31;
    din_1  = 29;
    din_2  = 27;
    din_3  = 25;
    din_4  = 23;
    din_5  = 21;
    din_6  = 19;
    din_7  = 17;
    din_8  = 15;
    din_9  = 13;
    din_10 = 11;
    din_11 = 9;
    din_12 = 7;
    din_13 = 5;
    din_14 = 3;
    din_15 = 1;
    din_16 = 2;
    din_17 = 2;
    din_18 = 4;
    din_19 = 4;
    din_20 = 4;
    din_21 = 4;
    din_22 = 8;
    din_23 = 16;
    din_24 = 8;
    din_25 = 16;
    din_26 = 32;
    din_27 = 32;
    din_28 = 0;
    din_29 = 10;
    din_30 = 20;
    din_31 = 30;
    vld_in = 1'b1;
    @(posedge clk);
    vld_in = 1'b0;
    repeat(20) begin
        din_0  = $random%9'h100;
        din_1  = $random%9'h100;
        din_2  = $random%9'h100;
        din_3  = $random%9'h100;
        din_4  = $random%9'h100;
        din_5  = $random%9'h100;
        din_6  = $random%9'h100;
        din_7  = $random%9'h100;
        din_8  = $random%9'h100;
        din_9  = $random%9'h100;
        din_10 = $random%9'h100;
        din_11 = $random%9'h100;
        din_12 = $random%9'h100;
        din_13 = $random%9'h100;
        din_14 = $random%9'h100;
        din_15 = $random%9'h100;
        din_16 = $random%9'h100;
        din_17 = $random%9'h100;
        din_18 = $random%9'h100;
        din_19 = $random%9'h100;
        din_20 = $random%9'h100;
        din_21 = $random%9'h100;
        din_22 = $random%9'h100;
        din_23 = $random%9'h100;
        din_24 = $random%9'h100;
        din_25 = $random%9'h100;
        din_26 = $random%9'h100;
        din_27 = $random%9'h100;
        din_28 = $random%9'h100;
        din_29 = $random%9'h100;
        din_30 = $random%9'h100;
        din_31 = $random%9'h100;
        vld_in = 1'b1;
        @(posedge clk);
        // vld_in = 1'b0;
    end
    repeat(4) @(posedge clk);
    $finish(2);
end

sort_32_u8 
#(
    .W_DATA (W_DATA ),
    .NUM    (NUM    )
)
u_sort_32_u8(
    .clk     (clk     ),
    .rst_n   (rst_n   ),
    .vld_in  (vld_in  ),
    .din_0   (din_0  ),
    .din_1   (din_1  ),
    .din_2   (din_2  ),
    .din_3   (din_3  ),
    .din_4   (din_4  ),
    .din_5   (din_5  ),
    .din_6   (din_6  ),
    .din_7   (din_7  ),
    .din_8   (din_8  ),
    .din_9   (din_9  ),
    .din_10  (din_10 ),
    .din_11  (din_11 ),
    .din_12  (din_12 ),
    .din_13  (din_13 ),
    .din_14  (din_14 ),
    .din_15  (din_15 ),
    .din_16  (din_16 ),
    .din_17  (din_17 ),
    .din_18  (din_18 ),
    .din_19  (din_19 ),
    .din_20  (din_20 ),
    .din_21  (din_21 ),
    .din_22  (din_22 ),
    .din_23  (din_23 ),
    .din_24  (din_24 ),
    .din_25  (din_25 ),
    .din_26  (din_26 ),
    .din_27  (din_27 ),
    .din_28  (din_28 ),
    .din_29  (din_29 ),
    .din_30  (din_30 ),
    .din_31  (din_31 ),
    .vld_out (vld_out ),
    .dout_0  (dout_0 ),
    .dout_1  (dout_1 ),
    .dout_2  (dout_2 ),
    .dout_3  (dout_3 ),
    .dout_4  (dout_4 ),
    .dout_5  (dout_5 ),
    .dout_6  (dout_6 ),
    .dout_7  (dout_7 ),
    .dout_8  (dout_8 ),
    .dout_9  (dout_9 ),
    .dout_10 (dout_10),
    .dout_11 (dout_11),
    .dout_12 (dout_12),
    .dout_13 (dout_13),
    .dout_14 (dout_14),
    .dout_15 (dout_15),
    .dout_16 (dout_16),
    .dout_17 (dout_17),
    .dout_18 (dout_18),
    .dout_19 (dout_19),
    .dout_20 (dout_20),
    .dout_21 (dout_21),
    .dout_22 (dout_22),
    .dout_23 (dout_23),
    .dout_24 (dout_24),
    .dout_25 (dout_25),
    .dout_26 (dout_26),
    .dout_27 (dout_27),
    .dout_28 (dout_28),
    .dout_29 (dout_29),
    .dout_30 (dout_30),
    .dout_31 (dout_31)
);
endmodule
`default_nettype wire